1. Field of the Invention
The present invention relates to a method for manufacturing an SOI wafer, more specifically it relates to an improvement in a method for manufacturing an SOI wafer in which an active layer wafer and a support wafer are bonded together.
This application claims priority from Japanese Patent Application No.2004-350286 filed on Dec. 2, 2004, the content of which is incorporated herein by reference.
2. Background Art
Compared with conventional silicon wafers, SOI (Silicon On Insulator) wafers having an SOI layer have advantages such as providing a separation between elements and a reduction in parasitic capacitance between elements and a substrate, and having the capability to form a three-dimensional configuration; thereby the SOI wafers are used for high speed, low power consumption LSI circuits. An examples of one of the methods for manufacturing an SOI wafer is a bonding method in which an oxide film is formed in at least one of two silicon wafers and the silicon wafers are bonded, and then the bonded wafer is ground and polished so as to form an SOI layer.
Regarding the bonding method, the SOI wafer may be manufactured, for example, as follows as described in Patent Document 1. At first, an active layer wafer of which one surface is mirror-polished and a support wafer of which one surface is mirror-polished are prepared. Next, an insulating film (an oxide film) having a predetermined thickness is formed in a surface (a mirror-polished surface) of the active layer wafer. And then, the active layer wafer and the support wafer are bonded together to form a bonded wafer such that the surface (the mirror-polished surface) in which the oxide film is formed and the surface (the mirror surface) of the support wafer are used as bonding surfaces.
After the bonding, the bonded wafer is subjected to a heat treatment so as to enhance the bonding strength between the active layer wafer and the support wafer. After this, a portion of the active layer wafer is ground and polished; thereby, an SOI wafer having an SOI layer of a predetermined thickness can be obtained.
When the bonded wafer is subjected to the heat treatment for bonding enhancement, the bonded wafer is loaded on a wafer boat. Generally, a contact surface contacting with the wafer boat is on the support wafer side.
As a result, when the bonded wafer is subjected to the heat treatment for bonding enhancement, slip dislocations occur in the support wafer due to the contact with the wafer boat. In detail, weight of the bonded wafer is concentrated on a portion contacting with the wafer boat, such as a portion of an outer circumference of the support wafer. This generates an internal stress in the wafer exceeding a critical shearing stress, thereby causing the slip dislocations in that portion contacting with the wafer boat in the support wafer. As a result, the mechanical strength of the SOI wafer is deteriorated by the slip dislocations occurring in the support wafer.
Patent Document 1: Japanese Unexamined Patent Application, First Publication No. 2001-44398